Texas Instruments, OMAP3530/25 pdf datasheet download

OMAP3530/25 Applications Processor

1 OMAP3530/25 Applications Processor

1.1.Features
OMAP3530/25 Applications Processor: – Additional C64x+™ Enhancements
– OMAP™ 3 Architecture · Protected Mode Operation
– MPU Subsystem · Exceptions Support for Error Detection
· Up to 720-MHz ARM Cortex™-A8 Core and Program Redirection
· NEON™ SIMD Coprocessor · Hardware Support for Modulo Loop – High Performance Image, Video, Audio Operation
(IVA2.2™) Accelerator Subsystem · C64x+ L1/L2 Memory Architecture
· Up to 520-MHz TMS320C64x+™ DSP – 32K-Byte L1P Program RAM/Cache (Direct
Core Mapped)
· Enhanced Direct Memory Access – 80K-Byte L1D Data RAM/Cache (2-Way
(EDMA) Controller (128 Independent Set-Associative)
Channels) – 64K-Byte L2 Unified Mapped RAM/Cache
· Video Hardware Accelerators (4-Way Set-Associative)
– POWERVR SGX™ Graphics Accelerator – 32K-Byte L2 Shared SRAM and 16K-Byte L2
(OMAP3530 Device Only) ROM
· Tile Based Architecture Delivering up to · C64x+ Instruction Set Features
10 MPoly/sec – Byte-Addressable (8-/16-/32-/64-Bit Data)
· Universal Scalable Shader Engine: – 8-Bit Overflow Protection
Multi-threaded Engine Incorporating – Bit-Field Extract, Set, Clear
Pixel and Vertex Shader Functionality – Normalization, Saturation. Bit-Counting
· Industry Standard API Support: – Compact 16-Bit Instructions OpenGLES 1.1 and 2.0, OpenVG1.0 – Additional Instructions to Support Complex · Fine Grained Task Switching, Load Multiplies Balancing, and Power Management
· Programmable High Quality Image · ARM Cortex™-A8 Core
Anti-Aliasing – ARMv7 Architecture
– Fully Software-Compatible With C64x and · Trust Zone®
ARM9™ · Thumb®-2
– Commercial and Extended Temperature · MMU Enhancements
Grades – In-Order, Dual-Issue, Superscalar
· Advanced Very-Long-Instruction-Word (VLIW) Microprocessor Core
TMS320C64x+™ DSP Core – NEON™ Multimedia Architecture
– Eight Highly Independent Functional Units – Over 2x Performance of ARMv6 SIMD
· +Six ALUs (32-/40-Bit), Each Supports – Supports Both Integer and Floating Point
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit SIMD
Arithmetic per Clock Cycle – Jazelle® RCT Execution Environment
· Two Multipliers Support Four 16 x 16-Bit Architecture
Multiplies (32-Bit Results) per Clock – Dynamic Branch Prediction with Branch
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Target Address Cache, Global History
Results) per Clock Cycle Buffer, and 8-Entry Return Stack
– Load-Store Architecture With Non-Aligned – Embedded Trace Macrocell (ETM) Support
Support for Non-Invasive Debug
– 64 32-Bit General-Purpose Registers · ARM Cortex™-A8 Memory Architecture:
– Instruction Packing Reduces Code Size – 16K-Byte Instruction Cache (4-Way
– All Instructions Conditional Set-Associative)

1.2.Description

OMAP3530 and OMAP3525 high-performance, applications processors are based on the enhanced
OMAP™ 3 architecture.
The OMAP™ 3 architecture is designed to provide best-in-class video, image, and graphics processing
sufficient to support the following:
· Streaming video
· 3D mobile gaming
· Video conferencing
· High-resolution still image
The device supports high-level operating systems (OSs), such as:
· Linux
· Windows CE
This OMAP device includes state-of-the-art power-management techniques required for high-performance
mobile products.
The following subsystems are part of the device:
· Microprocessor unit (MPU) subsystem based on the ARM Cortex™-A8 microprocessor
· IVA2.2 subsystem with a C64x+ digital signal processor (DSP) core
· POWERVR SGX™ subsystem for 3D graphics acceleration to support display and gaming effects
(3530 only)
· Camera image signal processor (ISP) that supports multiple formats and interfacing options connected
to a wide variety of image sensors
· Display subsystem with a wide variety of features for multiple concurrent image manipulation, and a
programmable interface supporting a wide variety of displays. The display subsystem also supports
NTSC/PAL video out.
· Level 3 (L3) and level 4 (L4) interconnects that provide high-bandwidth data transfers for multiple
initiators to the internal and external memory controllers and to on-chip peripherals
The device also offers:
· A comprehensive power and clock-management scheme that enables high-performance, low-power
operation, and ultralow-power standby features. The device also supports SmartReflex™ adaptative
voltage control. This power management technique for automatic control of the operating voltage of a
module reduces the active power consumption.
· Memory stacking feature using the package-on-package (POP) implementation (CBB and CBC
packages only)
OMAP30/25 devices are available in a 515-pin s-PBGA package (CBB suffix), 515-pin s-PBGA package
(CBC suffix), and a 423-pin s-PBGA package (CUS suffix). Some features of the CBB and CBC packages
are not available in the CUS package.

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