sn74hc139.pdf
Targeted Specifically for High-Speed
Memory Decoders and Data-Transmission
Systems
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 80-μA Max ICC
Typical tpd = 10 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 μA Max
Incorporate Two Enable Inputs to Simplify
Cascading and/or Data Reception
description/ordering information
The ’HC139 devices are designed for
high-performance memory-decoding or
data-routing applications requiring very short
propagation delay times. In high-performance
memory systems, these decoders can minimize
the effects of system decoding. When employed
with high-speed memories utilizing a fast enable
circuit, the delay time of these decoders and the
enable time of the memory usually are less than
the typical access time of the memory. This means
that the effective system delay introduced by the
decoders is negligible.
Click here to download sn74hc139 Texas Instruments TI pdf datasheet
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