Sunday, August 5, 2012

Texas Instruments TMS320DM642 pdf datasheet download


Video/Imaging Fixed-Point Digital Signal Processor

1 TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor
• High-Performance Digital Media Processor – 1024M-Byte Total Addressable External
– 2-, 1.67-, 1.39-ns Instruction Cycle Time Memory Space
– 500-, 600-, 720-MHz Clock Rate • Enhanced Direct-Memory-Access (EDMA)
– Eight 32-Bit Instructions/Cycle Controller (64 Independent Channels)
– 4000, 4800, 5760 MIPS • 10/100 Mb/s Ethernet MAC (EMAC)
– Fully Software-Compatible With C64x™ – IEEE 802.3 Compliant
• VelociTI.2™ Extensions to VelociTI™ – Media Independent Interface (MII)
Advanced Very-Long-Instruction-Word (VLIW) – 8 Independent Transmit (TX) Channels and 1
TMS320C64x™ DSP Core Receive (RX) Channel
– Eight Highly Independent Functional Units • Management Data Input/Output (MDIO)
With VelociTI.2™ Extensions: • Three Configurable Video Ports
• Six ALUs (32-/40-Bit), Each Supports – Providing a Glueless I/F to Common Video
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Decoder and Encoder Devices
Arithmetic per Clock Cycle – Supports Multiple Resolutions/Video Stds
• Two Multipliers Support Four 16 x 16-Bit • VCXO Interpolated Control Port (VIC)
Multiplies (32-Bit Results) per Clock – Supports Audio/Video Synchronization
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit • Host-Port Interface (HPI) [32-/16-Bit]
Results) per Clock Cycle • 32-Bit/66-MHz, 3.3-V Peripheral Component
– Load-Store Architecture With Non-Aligned Interconnect (PCI) Master/Slave Interface
Support Conforms to PCI Specification 2.2
– 64 32-Bit General-Purpose Registers • Multichannel Audio Serial Port (McASP)
– Instruction Packing Reduces Code Size – Eight Serial Data Pins
– All Instructions Conditional – Wide Variety of I2S and Similar Bit Stream
• Instruction Set Features Formats
– Byte-Addressable (8-/16-/32-/64-Bit Data) – Integrated Digital Audio I/F Transmitter
– 8-Bit Overflow Protection Supports S/PDIF, IEC60958-1, AES-3, CP-430
– Bit-Field Extract, Set, Clear Formats
– Normalization, Saturation, Bit-Counting • Inter-Integrated Circuit ( I2C Bus™)
– VelociTI.2™ Increased Orthogonality • Two Multichannel Buffered Serial Ports
• L1/L2 Memory Architecture • Three 32-Bit General-Purpose Timers
– 128K-Bit (16K-Byte) L1P Program Cache • Sixteen General-Purpose I/O (GPIO) Pins
(Direct Mapped) • Flexible PLL Clock Generator
– 128K-Bit (16K-Byte) L1D Data Cache (2-Way • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
Set-Associative) • 548-Pin Ball Grid Array (BGA) Package
– 2M-Bit (256K-Byte) L2 Unified Mapped (GDK and ZDK Suffixes), 0.8-mm Ball Pitch
RAM/Cache (Flexible RAM/Cache Allocation) • 548-Pin Ball Grid Array (BGA) Package
• Endianess: Little Endian, Big Endian (GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch
• 64-Bit External Memory Interface (EMIF) • 0.13-μm/6-Level Cu Metal Process (CMOS)
– Glueless Interface to Asynchronous • 3.3-V I/O, 1.2-V Internal (-500)
Memories (SRAM and EPROM) and • 3.3-V I/O, 1.4-V Internal (A-500, A-600, -600,
Synchronous Memories (SDRAM, SBSRAM, -720)

The TMS320C64x™ DSPs (including the TMS320DM642 device) are the highest-performance fixed-point
DSP generation in the TMS320C6000™ DSP platform. The TMS320DM642 (DM642) device is based on
the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW)
architecture (VelociTI.2™) developed by Texas Instruments (TI), making these DSPs an excellent choice
for digital media applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.
With performance of up to 5760 million instructions per second (MIPS) at a clock rate of 720 MHz, the
DM642 device offers cost-effective solutions to high-performance DSP programming challenges. The
DM642 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of
array processors. The C64x™ DSP core processor has 64 general-purpose registers of 32-bit word length
and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic
units (ALUs)—with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units
include new instructions to accelerate the performance in video and imaging applications and extend the
parallelism of the VelociTI™ architecture. The DM642 can produce four 16-bit multiply-accumulates
(MACs) per cycle for a total of 2880 million MACs per second (MMACS), or eight 8-bit MACs per cycle for
a total of 5760 MMACS. The DM642 DSP also has application-specific hardware logic, on-chip memory,
and additional on-chip peripherals similar to the other C6000™ DSP platform devices.
The DM642 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals.
The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is
a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 2-Mbit memory
space that is shared between program and data space. L2 memory can be configured as mapped
memory, cache, or combinations of the two. The peripheral set includes: three configurable video ports; a
10/100 Mb/s Ethernet MAC (EMAC); a management data input/output (MDIO) module; a VCXO
interpolated control port (VIC); one multichannel buffered audio serial port (McASP0); an inter-integrated
circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose
timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component
interconnect (PCI); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event
generation modes; and a 64-bit glueless external memory interface (EMIFA), which is capable of
interfacing to synchronous and asynchronous memories and peripherals.
The DM642 device has three configurable video port peripherals (VP0, VP1, and VP2). These video port
peripherals provide a glueless interface to common video decoder and encoder devices. The DM642
video port peripherals support multiple resolutions and video standards (e.g., CCIR601, ITU-BT.656,
BT.1120, SMPTE 125M, 260M, 274M, and 296M).
These three video port peripherals are configurable and can support either video capture and/or video
display modes. Each video port consists of two channels — A and B with a 5120-byte capture/display
buffer that is splittable between the two channels.
For more details on the Video Port peripherals, see the TMS320C64x DSP Video Port/VCXO Interpolated
Control (VIC) Port Reference Guide (literature number SPRU629).
The McASP0 port supports one transmit and one receive clock zone, with eight serial data pins which can
be individually allocated to any of the two zones. The serial port supports time-division multiplexing on
each pin from 2 to 32 time slots. The DM642 has sufficient bandwidth to support all 8 serial data pins
transmitting a 192-kHz stereo signal. Serial data in each zone may be transmitted and received on
multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC
Sound (I2S) format.
In addition, the McASP0 transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3,
CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of
user data and channel status fields.
McASP0 also provides extensive error-checking and recovery features, such as the bad clock detection
circuit for each high-frequency master clock which verifies that the master clock is within a programmed
frequency range.

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