spns177a.pdf
| 1 RM48L952 16/32-Bit RISC Flash Microcontroller | |
| 1.1 Features | |
| High-Performance Microcontroller for Safety " | Multiple Communication Interfaces " |
| Critical Applications | ?10/100 Mbps Ethernet MAC (EMAC) |
| ?Dual CPU抯 running in lockstep | IEEE 802.3 compliant (3.3V-I/O only) " |
| ?ECC on flash and RAM interfaces | Supports MII and MDIO " |
| ?Built-In Self Test for CPU and on-chip RAMs | ?USB |
| ?Error Signaling Module with Error Pin | 2-port USB Specification |
| ?Voltage and Clock Monitoring | compatible host controller, based on the |
| ARM?Cortex" ?R4F 32-bit RISC CPU " | OHCI Specification for USB, release 1.0 |
| ?Efficient 1.66DMIPS/MHz with 8-stage pipeline ?FPU with Single/Double Precision ?12-Region Memory Protection Unit ?Open Architecture with 3rd Party Support Operating Conditions ?Up to 220MHz System Clock ?Core Supply Voltage (VCC): 1.2V nominal ?I/O Supply Voltage (VCCIO): 3.3V nominal " Integrated Memory ?3MB Program Flash with ECC ?256KB RAM with ECC ?64KB Flash for emulated EEPROM " | One full-speed USB device compatible with the USB Specification |
| 16-bit External Memory Interface " Common Platform Architecture " | Compliant to LIN protocol version 2.1 ?Standard Serial Communication Interface " |
| ?Consistent memory map across family | (SCI) |
| ?Real-Time Interrupt Timer (RTI) OS Timer | Two High-End Timer Modules (N2HET) " |
| ?96-channel Vectored Interrupt Module (VIM) | ?N2HET1: 32 programmable channels |
| ?2-channel Cyclic Redundancy Checker (CRC) | ?N2HET2: 20 programmable channels |
| Direct Memory Access (DMA) Controller " | ?160 Word Instruction RAM with parity |
| ?16 Channels and 32 Control Packets | protection each |
| ?Parity protection for control packet RAM | ?Each includes Hardware Angle Generator |
| ?DMA Accesses Protected by Dedicated MPU | ?Dedicated Transfer Unit for each N2HET |
| Frequency-Modulated Phase-Locked-Loop " | (HTU) |
| (FMPLL) with Built-In Slip Detector | Two 10/12-bit Multi-Buffered ADC Modules " |
| Separate Non-Modulating PLL " | ?ADC1: 24 channels |
| IEEE 1149.1 JTAG | Boundary Scan and ARM " |
| CoreSight Components | ?16 shared channels |
| JTAG Security Module " | ?64 result buffers with parity protection each |
| Trace and Calibration Capabilities " | Packages " |
| ?Embedded Trace Macrocell (ETM-R4) | ?144-pin Quad Flatpack (PGE) [Green] |
| ?Data Modification Module (DMM) | ?337-Ball Grid Array (ZWT) [Green] |
| ?RAM Trace Port (RTP) | |
| ?Parameter Overlay Module (POM) |
1.2 Applications
• Industrial Safety Applications
– Industrial Automation
– Safe PLC's (Programmable Logic Controllers)
– Power Generation and Distribution
– Turbines and Windmills
– Elevators and Escalators
• Medical Applications
– Ventilators
– Defibrillators
– Infusion and Insulin pumps
– Radiation therapy
– Robotic surgery
1.3 Description
The RM48L952 is a high performance microcontroller family for safety systems. The safety architecture
includes Dual CPUs in lockstep, CPU and Memory Built-In Self Test (BIST) logic, ECC on both the Flash
and the data SRAM, parity on peripheral memories, and loop back capability on peripheral IOs.
The RM48L952 integrates the ARM® Cortex™-R4F Floating Point CPU which offers an efficient
1.66DMIPS/MHz, and has configurations which can run up to 220 MHz, providing up to 365 DMIPS. The
device supports the little-endian [LE32] format.
The RM48L952 has 3MB integrated Flash and 256KB data RAM with single bit error correction and
double bit error detection. The flash memory on this device is a nonvolatile, electrically erasable and
programmable memory implemented with a 64-bit-wide data bus interface. The flash operates on a 3.3V
supply input (same level as I/O supply) for all read, program and erase operations. When in pipeline
mode, the flash operates with a system clock frequency of up to 220MHz. The SRAM supports singlecycle
read/write accesses in byte, halfword, and word modes.
The RM48L952 device features peripherals for real-time control-based applications, including two Next
Generation High End Timer (N2HET) timing coprocessors with up to 44 total IO terminals and a 12-bit
Analog-to-Digital converter supporting up to 24 inputs.
DatasheetDoc-Texas Instruments TI pdf datasheet download
0 comments:
Post a Comment