sn74lvc1g10.pdf
Features
| · Available in the Texas Instruments NanoFree Package · Supports 5-V VCC Operation " | Operation · Latch-Up Performance Exceeds 100 mA per JESD 78, Class II |
| · Inputs Accept Voltages to 5.5 V | · ESD Protection Exceeds JESD 22 |
| · Max tpd of 3.8 ns at 3.3 V · Low Power Consumption, 10-mA Max ICC | – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) |
| · ±24-mA Output Drive at 3.3 V | – 1000-V Charged Device Model (C101) |
| · Ioff Supports Partial-Power-Down Mode |
DESCRIPTION/ORDERING INFORMATION
SN74LVC1G10
SINGLE 3-INPUT POSITIVE-NAND GATE
SCES486D–SEPTEMBER 2003–REVISED JANUARY 2007
· Available in the Texas Instruments Operation
NanoFree™ Package · Latch-Up Performance Exceeds 100 mA per
· Supports 5-V VCC Operation JESD 78, Class II
· Inputs Accept Voltages to 5.5 V · ESD Protection Exceeds JESD 22
· Max tpd of 3.8 ns at 3.3 V – 2000-V Human-Body Model (A114-A)
· Low Power Consumption, 10-mA Max ICC – 200-V Machine Model (A115-A)
· ±24-mA Output Drive at 3.3 V – 1000-V Charged Device Model (C101)
· Ioff Supports Partial-Power-Down Mode
The SN74LVC1G10 performs the Boolean function Y = A · B · C or Y = A + B + C in positive logic.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
DatasheetDoc-Texas Instruments TI pdf datasheet download
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