tms320f28055.pdf
1 TMS320F2805x ( Piccolo™) MCUs
| 1.1 Features | |
| Highlights " | Programmable Control Law Accelerator (CLA) " |
| – High-Efficiency 32-Bit CPU ( TMS320C28x) " | – 32-Bit Floating-Point Math Accelerator |
| – 60-MHz Device – Single 3.3-V Supply – Integrated Power-on and Brown-out Resets – Two Internal Zero-pin Oscillators – Up to 42 Multiplexed GPIO Pins – Three 32-Bit CPU Timers – On-Chip Flash, SARAM, Message RAM, OTP, CLA Data ROM, Boot ROM, Secure ROM | – Executes Code Independently of the Main CPU Low Device and System Cost: – Single 3.3-V Supply – No Power Sequencing Requirement – Integrated Power-on Reset and Brown-out Reset – Low Power " |
| Memory | – No Analog Support Pins |
| – Dual-Zone Security Module | Clocking: " |
| – Serial Port Peripherals (SCI/SPI/I2C/eCAN) | – Two Internal Zero-pin Oscillators |
| – Enhanced Control Peripherals Enhanced Pulse Width Modulator (ePWM) " Enhanced Capture (eCAP) " Enhanced Quadrature Encoder Pulse " | – On-Chip Crystal Oscillator/External Clock Input – Dynamic PLL Ratio Changes Supported – Watchdog Timer Module |
| (eQEP) | – Missing Clock Detection Circuitry |
| – Analog Peripherals One 12-Bit Analog-to-Digital Converter (ADC) " One On-Chip Temperature Sensor " Up to Seven Comparators With up to Three Integrated Digital-to-Analog Converters (DACs) " | Up to 42 Individually Programmable |
| One Buffered Reference DAC " | On-Chip Memory " |
| Up to Four Programmable Gain Amplifiers (PGAs) " | – Flash, SARAM, Message RAM, OTP, CLA Data ROM, Boot ROM, Secure ROM Available |
| Up to Four Digital Filters " | 128-Bit Security Key and Lock " |
| – 80-Pin Package | – Protects Secure Memory Blocks |
| High-Efficiency 32-Bit CPU ( TMS320C28x") " | – Prevents Firmware Reverse Engineering |
| – 60 MHz (16.67-ns Cycle Time) | Serial Port Peripherals " |
| – 16 x 16 and 32 x 32 MAC Operations | – Three SCI (UART) Modules |
| – 16 x 16 Dual MAC | – One SPI Module |
| – Harvard Bus Architecture | – One Inter-Integrated-Circuit (I2C) Bus |
| – Atomic Operations – Fast Interrupt Response and Processing – Unified Memory Programming Model – Code-Efficient (in C/C++ and Assembly) Endianness: Little Endian " | – One Enhanced Controller Area Network (eCAN) Bus Advanced Emulation Features – Analysis and Breakpoint Functions – Real-Time Debug via Hardware " |
| | |
| 80-Pin PN Low-Profile Quad Flatpack (LQFP) " |
1.2 Description
The F2805x Piccolo™ family of microcontrollers provides the power of the C28x™ core and Control Law
Accelerator (CLA) coupled with highly integrated control peripherals in low pin-count devices. This family
is code-compatible with previous C28x-based code, as well as providing a high level of analog integration.
An internal voltage regulator allows for single rail operation. Analog comparators with internal 6-bit
references have been added and can be routed directly to control the PWM outputs. The ADC converts
from 0 to 3.3-V fixed full scale range and supports ratio-metric VREFHI/VREFLO references. The ADC
interface has been optimized for low overhead/latency.
The Analog Front End (AFE) contains up to seven comparators with up to three integrated Digital-to-
Analog Converters (DACs), one VREFOUT-buffered DAC, up to four Programmable Gain Amplifiers
(PGAs), and up to four digital filters. The Programmable Gain Amplifiers (PGAs) are capable of amplifying
the input signal in three discrete gain modes. The actual gain itself depends on the resistors defined by
the user at the bipolar input end. The actual number of AFE peripherals will depend upon the 2805x
device number. See Table 2-1 for more details.
DatasheetDoc-Texas Instruments TI pdf datasheet download
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