sn74lvc1g175.pdf
| · Available in the Texas Instruments NanoFree Package " | · Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II |
| · Supports 5-V VCC Operation | · ESD Protection Exceeds JESD 22 |
| · Inputs Accept Voltages to 5.5 V | – 2000-V Human-Body Model (A114-A) |
| · Max tpd of 4.3 ns at 3.3 V | – 200-V Machine Model (A115-A) |
| · Low Power Consumption, 10-mA Max ICC | – 1000-V Charged-Device Model (C101) |
| · ±24-mA Output Drive at 3.3 V | |
| · Ioff Supports Partial-Power-Down Mode Operation |
DESCRIPTION/ORDERING INFORMATION
SN74LVC1G175
www.ti.com ........................................................................................................................................................ SCES560E–MARCH 2004–REVISED JUNE 2008
SINGLE D-TYPE FLIP-FLOP WITH ASYNCHRONOUS CLEAR
2· Available in the Texas Instruments NanoFree™ · Latch-Up Performance Exceeds 100 mA Per
Package JESD 78, Class II
· Supports 5-V VCC Operation · ESD Protection Exceeds JESD 22
· Inputs Accept Voltages to 5.5 V – 2000-V Human-Body Model (A114-A)
· Max tpd of 4.3 ns at 3.3 V – 200-V Machine Model (A115-A)
· Low Power Consumption, 10-mA Max ICC – 1000-V Charged-Device Model (C101)
· ±24-mA Output Drive at 3.3 V
· Ioff Supports Partial-Power-Down Mode
Operation
This single D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G175 has an asynchronous clear (CLR) input. When CLR is high, data from the input pin (D) is
transferred to the output pin (Q) on the clock's (CLK) rising edge. When CLR is low, Q is forced into the low
state, regardless of the clock edge or data on D.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
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