spns157c.pdf
| 1 Features | |
| ?High-Performance Automotive Grade | ?Communication Interfaces |
| Microcontroller with Safety Features | ?Two CAN Controllers |
| ?Full Automotive Temperature Range | ?One with 32 mailboxes, one with 16 |
| ?ECC on Flash and SRAM | ?Parity on mailbox RAM |
| ?CPU and Memory BIST (Built-In Self Test) | ?Two Multi-buffered Serial Peripheral |
| ?ARM Cortex-M3 32-Bit RISC CPU " | Interface (MibSPI) |
| ?Efficient 1.2 DMIPS/MHz | ?12 total chip selects |
| ?Optimized Thumb2 Instruction Set | ?64 buffers with parity on each |
| ?Memory Protection Unit (MPU) | ?Two UART (SCI) interfaces |
| ?Open Architecture With Third-Party Support | ?H/W Support for Local Interconnect |
| ?Built-In Debug Module | Network (LIN 2.1 master mode) |
| ?Operating Features | ?High-End Timer (HET) |
| ?Up to 80MHz System Clock | ?Up to 18 Programmable I/O Channels |
| ?Single 3.3V Supply Voltage | ?64 Word Instruction RAM with parity |
| ?Integrated Memory | ?10-Bit Multi-Buffered ADCs (MibADC) |
| ?640KB Total Program Flash with ECC | ?Up to 16 ADC Input channels |
| ?Support for Flash EEPROM Emulation | ?64 Result FIFO Buffer with parity |
| ?64K-Byte Static RAM (SRAM) with ECC | ?1.55uS total conversion time |
| ?Key Peripherals | ?Calibration and Self Test features |
| ?High-End Timer, MibADC, CAN, MibSPI | ?On-Chip Scan-Base Emulation Logic |
| ?Common TMS470M/570 Platform Architecture ?Consistent Memory Map across the family ?Real-Time Interrupt Timer (RTI) ?Digital Watchdog ?Vectored Interrupt Module (VIM) ?Cyclic Redundancy Checker (CRC) ?Frequency-Modulated Zero-Pin Phase-Locked Loop (FMzPLL)-Based Clock Module ?Oscillator and PLL clock monitor | ?IEEE Standard 1149.1 (JTAG) Test-Access Port and Boundary Scan ?Packages supported ?100-Pin Plastic Quad Flatpack (PZ Suffix) ?Green/Lead-Free ?Development Tools Available ?Development Boards ?Code Composer Studio?Integrated Development Environment (IDE) |
| ?Up to 51 Peripheral IO pins ?4 Dedicated GIO -w/ External Interrupts ?Programmable External Clock (ECLK) | ?HET Assembler and Simulator ?nowFlash?Flash Programming Tool ?Community Resources |
1.2 Description
The TMS470MF06607 device is a member of the Texas Instruments TMS470M family of Automotive
Grade 16/32-bit reduced instruction set computer (RISC) microcontrollers. The TMS470M microcontrollers
offer high performance utilizing the high efficiency ARM Cortex™-M3 16/32-bit RISC central processing
unit (CPU), resulting in a high instruction throughput while maintaining greater code efficiency.
High-end embedded control applications demand more performance from their controllers while
maintaining low costs. The TMS470M microcontroller architecture offers solutions to these performance
and cost demands while maintaining low power consumption.
The TMS470MF06607 device contains the following:
• 16/32-Bit RISC CPU Core
• 640K-Byte Total Flash with SECDED ECC
– 512K-Byte Program Flash
– 128K- Byte Flash for additional program space or EEPROM Emulation
• 64K-Byte Static RAM (SRAM) with SECDED ECC
• Real-Time Interrupt Timer (RTI)
• Vectored Interrupt Module (VIM)
• Hardware built-in self-test (BIST) checkers for SRAM (MBIST) and CPU (LBIST)
• 64-bit Cyclic Redundancy Checker (CRC)
• Frequency-Modulated Zero-Pin Phase-Locked Loop (FMzPLL)-Based Clock Module With Prescaler
• Two Multi-buffered Serial Peripheral Interfaces (MibSPI)
• Two UARTs (SCI) with Local Interconnect Network Interfaces (LIN)
• Two CAN Controller (DCAN)
• High-End Timer (HET)
• External Clock Prescale (ECP) Module
• One 16-Channel 10-Bit Multi-Buffered ADC (MibADC)
• Error Signaling Module (ESM)
• Four Dedicated General-Purpose I/O (GIO) Pins and 47 (2 of them are muxed with JTAG pins)
Additional Peripheral I/Os (100-Pin Package)
The TMS470M memory includes general-purpose SRAM supporting single-cycle read/write accesses in
byte, half-word, and word modes. The SRAM on the TMS470M devices can be protected by means of
ECC. This feature utilizes a single error correction and double error detection circuit (SECDED circuit) to
detect and optionally correct single bit errors as well as detect all dual bit and some multi-bit errors. This is
achieved by maintaining an 8-bit ECC checksum/code for each 64-bit double-word of memory space in a
separate ECC RAM memory space.
The flash memory on this device is a nonvolatile, electrically erasable and programmable memory. It is
implemented with a 144-bit wide data word (128-bit without ECC) and a 64-bit wide flash module interface.
The flash operates with a system clock frequency of up to 28 MHz. Pipeline mode, which allows linear
prefetching of flash data, enables a system clock of up to 80 MHz.
The enhanced real-time interrupt (RTI) module on the TMS470M devices has the option to be driven by
the oscillator clock. The digital watchdog (DWD) is a 25-bit resetable decrementing counter that provides a
system reset when the watchdog counter expires.
The TMS470M devices have six communication interfaces: two LIN/SCIs, two DCANs and two MibSPIs.
The LIN is the Local Interconnect Network standard and also supports an SCI mode. SCI can be used in a
full-duplex, serial I/O interface intended for asynchronous communication between the CPU and other
peripherals using the standard non-return-to-zero (NRZ) format. The DCAN uses a serial, multimaster
communication protocol that efficiently supports distributed real-time control with robust communication
DatasheetDoc-Texas Instruments TI pdf datasheet download
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