sn74lvc1g123.pdf
FEATURES
· Retriggerable for Very Long Output Pulses, up
| · Available in the Texas Instruments | to 100% Duty Cycle |
| NanoFree Package " | · Overriding Clear Terminates Output Pulse |
| · Supports 5-V VCC Operation | · Glitch-Free Power-Up Reset on Outputs |
| · Inputs Accept Voltages to 5.5 V | · Ioff Supports Partial-Power-Down Mode |
| · Max tpd of 8 ns at 3.3 V · Supports Mixed-Mode Voltage Operation on All Ports | Operation · Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II |
| · Schmitt-Trigger Circuitry on A and B Inputs | · ESD Protection Exceeds JESD 22 |
| for Slow Input Transition Rates | – 2000-V Human-Body Model (A114-A) |
| · Edge Triggered From Active-High or | – 200-V Machine Model (A115-A) |
| Active-Low Gated Logic Inputs | – 1000-V Charged-Device Model (C101) |
DESCRIPTION/ORDERING INFORMATION
SN74LVC1G123
SINGLE RETRIGGERABLE MONOSTABLE MULTIVIBRATOR
WITH SCHMITT-TRIGGER INPUTS
SCES586B–JULY 2004–REVISED JANUARY 2007
· Retriggerable for Very Long Output Pulses, up
· Available in the Texas Instruments to 100% Duty Cycle
NanoFree™ Package · Overriding Clear Terminates Output Pulse
· Supports 5-V VCC Operation · Glitch-Free Power-Up Reset on Outputs
· Inputs Accept Voltages to 5.5 V · Ioff Supports Partial-Power-Down Mode
· Max tpd of 8 ns at 3.3 V Operation
· Supports Mixed-Mode Voltage Operation on · Latch-Up Performance Exceeds 100 mA Per
All Ports JESD 78, Class II
· Schmitt-Trigger Circuitry on A and B Inputs · ESD Protection Exceeds JESD 22
for Slow Input Transition Rates – 2000-V Human-Body Model (A114-A)
· Edge Triggered From Active-High or – 200-V Machine Model (A115-A)
Active-Low Gated Logic Inputs – 1000-V Charged-Device Model (C101)
The SN74LVC1G123 is a single retriggerable monostable multivibrator designed for 1.65-V to 5.5-V VCC
operation.
This monostable multivibrator features output pulse-duration control by three methods. In the first method, the A
input is low, and the B input goes high. In the second method, the B input is high, and the A input goes low. In
the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.
The output pulse duration is programmed by selecting external resistance and capacitance values. The external
timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected
between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between
Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR low.
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input
pulse. The A and B inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition rates
with jitter-free triggering at the outputs.
Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A) or
high-level-active (B) input. Pulse duration can be reduced by taking CLR low. CLR can be used to override A or
B inputs. The input/output timing diagram illustrates pulse control by retriggering the inputs and early clearing.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
DatasheetDoc-Texas Instruments TI pdf datasheet download
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