sn74lvc1g3208.pdf
| Features | · Can Be Used in Three Combinations: |
| · Available in the Texas Instruments NanoStar and NanoFree" Packages " | – OR-AND Gate |
| – OR Gate | |
| · Supports 5-V VCC Operation | – AND Gate |
| · Inputs Accept Voltages to 5.5 V | · Ioff Supports Partial-Power-Down Mode |
| · Max tpd of 5 ns at 3.3 V | Operation |
| · Low Power Consumption, 10-mA Max ICC | · Latch-Up Performance Exceeds 100 mA Per |
| · ±24-mA Output Drive at 3.3 V | JESD 78, Class II |
| · Input Hysteresis Allows Slow Input Transition | · ESD Protection Exceeds JESD 22 |
| and Better Switching Noise Immunity at the | – 2000-V Human-Body Model (A114-A) |
| Input (Vhys = 250 mV Typ @ 3.3 V) | – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) |
DESCRIPTION/ORDERING INFORMATION
SN74LVC1G3208
SINGLE 3-INPUT POSITIVE OR-AND GATE
SCES605A–SEPTEMBER 2004–REVISED JUNE 2005
· Can Be Used in Three Combinations:
· Available in the Texas Instruments – OR-AND Gate
NanoStar™ and NanoFree™ Packages – OR Gate
· Supports 5-V VCC Operation – AND Gate
· Inputs Accept Voltages to 5.5 V · Ioff Supports Partial-Power-Down Mode
· Max tpd of 5 ns at 3.3 V Operation
· Low Power Consumption, 10-mA Max ICC · Latch-Up Performance Exceeds 100 mA Per
· ±24-mA Output Drive at 3.3 V JESD 78, Class II
· Input Hysteresis Allows Slow Input Transition · ESD Protection Exceeds JESD 22
and Better Switching Noise Immunity at the – 2000-V Human-Body Model (A114-A)
Input – 200-V Machine Model (A115-A)
(Vhys = 250 mV Typ @ 3.3 V) – 1000-V Charged-Device Model (C101)
This device is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G3208 is a single 3-input positive OR-AND gate. It performs the Boolean function Y = (A + B) × C
in positive logic.
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
By tying one input to GND or VCC, the SN74LVC1G3208 offers two more functions. When C is tied to VCC, this
device performs as a 2-input OR gate (Y = A + B). When A is tied to GND, the device works as a 2-input AND
gate (Y = B × C). This device also works as a 2-input AND gate when B is tied to GND (Y = A × C).
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
DatasheetDoc-Texas Instruments TI pdf datasheet download
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