sn74lvc1g126.pdf
| FEATURES | ||
| Available in the Texas Instruments NanoFree" Package " | Latch-Up Performance Exceeds 100 mA Per JESD 78 | Class II " |
| Supports 5-V VCC Operation " | ESD Protection Exceeds JESD 22 " | |
| Inputs Accept Voltages to 5.5 V " | – 2000-V Human-Body Model (A114-A) | |
| Max tpd of 3.7 ns at 3.3 V " Low Power Consumption | 10-μA Max ICC " | – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) |
| ±24-mA Output Drive at 3.3 V " | ||
| Ioff Supports Partial-Power-Down Mode Operation " |
DESCRIPTION/ORDERING INFORMATION
This single bus buffer gate is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G126 is a single line driver with a 3-state output. The output is disabled when the output-enable
(OE) input is low.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
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